`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineers: Brentton Garber, Georgii Tkachuk
// 
// Create Date: 17:28:56 05/01/2013 
// Design Name: instr_decoder
// Module Name: instr_decoder
// Project Name: Lab 3
// Target Devices: Xilinx Spartan6 XC6LX16-CS324 
// Tool versions: Xilinx ISE 14.2 
// Description: Decodes the data received from fifo, and executes the commands accordingly
//
// Revision: 1
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////

module instr_decoder(
	input [7:0] instr_data,
	input clk,
	input reset,
	input instr_exec,
	output wire [3:0] o_data,
	output wire [1:0] o_addr,
	output reg LDR,
	output reg SUM,
	output reg CMP,
	output reg MUL,
	output reg alu_en);

//split the instruction into fields:
wire [1:0] op;

// assign input data to variables
assign op =  instr_data[7:6];
assign o_addr = instr_data[5:4];
assign o_data =  instr_data[3:0];

// Keep track of our states
reg state = OFF;
reg next_state = OFF;

// ON/OFF parameters
parameter ON = 1'b1, 
			 OFF = 1'b0; 

// Always on positive edge of clock
always @(posedge clk or negedge reset) begin
	if(~reset) begin // On negedge reset, clear all registers
		LDR <= 0;
		SUM <= 0;
		CMP <= 0;
		MUL <= 0;
		alu_en <= 0;
	end
	else  if(instr_exec) begin // if there is an execute command
		// Set all op codes to 0
		LDR <= 0;
		SUM <= 0;
		CMP <= 0;
		MUL <= 0;
		alu_en <= 0;
		// Set the reg to 1 depending on the opcode, and enable the ALU if nessary
		case(op)
			2'b00: LDR <= 1;
			2'b01: begin 
				SUM <= 1;
				alu_en <= 1;
			end
			2'b10: begin 
				MUL <= 1;	
				alu_en <= 1;
			end
			2'b11: begin 
				CMP <= 1;
				alu_en <= 1;
			end
		endcase
	end
	else begin // if no command, set all registers to 0
		LDR <= 0;
		SUM <= 0;
		CMP <= 0;
		MUL <= 0;
		alu_en <= 0;
	end
	
end
endmodule
